/**
 * File              : system_regs.h
 * Author            : Major Lin <mingjie.lin@nxp.com>
 * Date              : 01.08.2019
 * Last Modified Date: 01.08.2019
 * Last Modified By  : Major Lin <mingjie.lin@nxp.com>
 */
#ifndef __SYSTEM_REGS_H_
#define __SYSTEM_REGS_H_
#include "common.h"
typedef struct NVIC_MemMap {
  uint32_t ISER[8];                                /**< Interrupt Set Enable Register n, array offset: 0x0, array step: 0x4 */
  uint8_t RESERVED_0[96];
  uint32_t ICER[8];                                /**< Interrupt Clear Enable Register n, array offset: 0x80, array step: 0x4 */
  uint8_t RESERVED_1[96];
  uint32_t ISPR[8];                                /**< Interrupt Set Pending Register n, array offset: 0x100, array step: 0x4 */
  uint8_t RESERVED_2[96];
  uint32_t ICPR[8];                                /**< Interrupt Clear Pending Register n, array offset: 0x180, array step: 0x4 */
  uint8_t RESERVED_3[96];
  uint32_t IABR[8];                                /**< Interrupt Active bit Register n, array offset: 0x200, array step: 0x4 */
  uint8_t RESERVED_4[224];
  uint8_t IP[106];                                 /**< Interrupt Priority Register 0..Interrupt Priority Register 105, array offset: 0x300, array step: 0x1 */
  uint8_t RESERVED_5[2710];
  uint32_t STIR[1];                                /**< Software Trigger Interrupt Register, array offset: 0xE00, array step: 0x4 */
} volatile *NVIC_MemMapPtr;

/* NVIC - Peripheral instance base addresses */
/** Peripheral NVIC base pointer */
#define NVIC_BASE_PTR                            ((NVIC_MemMapPtr)0xE000E100u)
#endif
